The present invention relates to a microprocessor system configured by connecting a memory and/or I/O having an n/2-bit data bus width to a microprocessor having an n-bit data bus width.
Semiconductor technology has developed in recent years to allow creation of a high-performance computer system through a combination of a microprocessor and its peripheral control LSIs (DMA controller, etc.) and has developed to the extent that computer systems can be designed with ease. Furthermore, 8-bit microprocessors are gradually being replaced with 16- and 32-bit microprocessors, and microprocessor capability has been reinforced. However, most currently available peripheral control LSIs are operated on an 8-bit operation basis. For example, when a 16-bit microprocessor controls a peripheral control LSI with an 8-bit data bus width, two byte transfer instructions are used in place of one word transfer instruction. In this manner, a programmer must create a program by considering combinations of the architecture of the system executable instructions (1-/2-/4-byte access instructions or the like). Since a word transfer instruction cannot be used in the 8-bit peripheral control LSI, existing software for 16-microprocessors must be rewritten such that a 16-bit word instruction is replaced with two byte transfer instructions.
The prior art will be described hereinafter. FIG. 1 is a block diagram of a conventional microprocessor system. The system comprises a microprocessor (.mu.CPU 8086) 1, a bus controller (BUS CTRLR) 2, a latch (LATCH) 3, a bus transceiver (TRANSCEIVER) 4, a memory and/or I/O (MEMORY AND/OR I/O) (to be referred to as a memory hereinafter) 5 having a 16-bit data bus width, and a system bus 6. The microprocessor 1 comprises, for example, a microprocessor 8086 available from Intel Corp., U.S.A. The microprocessor 1 receives a clock CLK and sends status data STS1 to the controller 2. Upon reception of the data STS1, the controller 2 supplies a read/write control signal STS to the memory 5 or the like.
The microprocessor 1 is connected to the latch 3 and the transceiver 4 through an address data bus ADR/DAT. The microprocessor 1 supplies an address signal to the latch 3 and a data signal to the transceiver 4. The latch 3 receives the address signal from the microprocessor and supplies an address ADDR to the memory 5. The transceiver 4 is connected to the memory through a data bus DATA and the bus 6 and transfers data from or to the memory 5. The controller 2 supplies a signal ALE to the latch 3 and a signal BDCTL to the transceiver 4. The signal ALE controls a latch timing of the address, and the signal BDCTL controls the input/output of the transceiver 4.
The operation of the microprocessor system will be described. FIGS. 2A to 2E are timing charts explaining a read cycle word transfer instruction starting from an even address in the circuit of FIG. 1. The machine cycle basically consists of clocks (CLK) T1, T2, T3 and T4, as shown in FIG. 2A. In the read cycle starting from the even address, the microprocessor 1 generates the address and the status data in response to the clock T1, as shown in FIG. 2B. The controller 2 supplies the signal ALE to the latch 3 in response to the status data, as shown in FIG. 2D. The controller 2 supplies the signal STS to the memory 5, as shown in FIG. 2C. The latch 3 latches the address in response to the signal ALE generated from the controller 2. Data of 16 bits is read out from the memory 5 onto the bus DATA, and the transceiver 4 sends the 16-bit data shown in FIG. 2B from the memory 5 onto the bus ADR/DAT by the control signal BDCTL shown in FIG. 2E from the bus controller 2.
The microprocessor 1 fetches the data at the trailing edge of the clock T3. In the word transfer instruction of the read cycle starting from an odd address, there are two access cycles. Data fetching is performed in the same manner as in the read cycle starting from an even address. However, in the first access cycle, the data corresponding to the start odd address is fetched as the most significant part of the 16-bit data. The address is then updated, and in the second access cycle, the data corresponding to an even address next to the start odd address is fetched as the least significant part. In this manner, 16-bit data is thus fetched by the microprocessor 1.
The above operation can be performed in the same manner as in the word transfer instruction of the write cycle. As is apparent from the above description, the prior art microprocessor system has a 16-byte boundary. Although one address has 1-byte data, the address has, as its objective, a memory of basically a 16-bit data bus switch. For this reason, the microprocessor system configuration is not flexible, resulting in inconvenience (see MEMORY ORGANIZATION of MICROPROCESSOR AND PERIPHERALS HANDBOOK 1983 published by Intel Corp. for further reference).